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preliminary aec q100 grade 1 compliant this is a product that has fixed target specifications but are subject ramtron international corporation to change pending characterization results . 1850 ramtron drive, c olorado springs, co 80921 (800) 545 - fram, (7 19) 481 - 7000 rev. 1.1 http://www.ramtron.com june 2011 page 1 of 12 fm 24cl64b - automotive temp. 64 k b serial 3v f - ram memory features 64 k bit ferroelectric nonvolatile ram ? organized as 8192 x 8 bits ? high endurance 10 trillion (10 1 3 ) read/writes ? nodelay? writes ? advanced high - reliability ferroelectric process fast two - wire serial interface ? up to 1 mhz maximum bus frequency ? direct hardware replacement for eeprom ? supports legacy timing for 100 khz & 400 khz low power consumption ? low voltage operation 3.0 - 3.6v ? 6 ? a standby current (+85 ? c) industry standard configurat ion ? automotive temperature - 40 ? c to +125 ? c o qualified to aec q100 specification ? 8 - pin green/rohs soic package description the fm 24cl 64b is a 64 kbit nonvolatile memory employing an advanced ferroelectric process. a ferroelectric random access memory o r f - ram is nonvolatile and performs reads and writes like a ram. it provide s reliable data retention for years while eliminating the complexities, overhead, and system level reliability problems caused by eeprom and other nonvolatile memories. the fm 24cl 64b performs write operations at bus speed. no write delays are incurred. the next bus cycle may commence immediately without the need for data polling. in addition, the product offers write endurance orders of magnitude higher than eeprom. also, f - ram exh ibits much lower power during writes than eeprom since write operations do not require an internally elevated power supply voltage for write circuits. these capabilities make the fm 24cl 64b ideal for nonvolatile memory applications requiring frequent or ra pid writes. examples range from data collection where the number of write cycles may be critical, to demanding industrial controls where the long write time of eeprom can cause data loss. the combination of features allows more frequent data writing with l ess overhead for the system. the fm 24cl 64b provides substantial benefits to users of serial eeprom, yet these benefits are available in a hardware drop - in repla cement. the device is available in industry stan dard 8 - pin soic package using a familiar two - w ire (i 2 c) protocol. the device is guaranteed over the automotive temperature range of - 40c to + 125 c. pin configuration pin name function a 0 - a2 device select address sda serial data/address scl serial clock wp write p rotect vdd supply voltage vss ground ordering information fm 24cl64b - g a green/rohs 8 - pin soic , automotive grade 1 fm 24cl64b - g a tr green/rohs 8 - pin soic, automotive grade 1 , tape & reel a 0 a 1 a 2 vss vdd wp scl sda 1 2 3 4 8 7 6 5
fm24cl64b - 64kb 3v i2c f - ram (automotive temp.) rev. 1.1 june 2 011 page 2 of 12 figure 1. fm 24cl 64b block d iagram pin description pin name type pin description a0 - a2 input device select addres s 0 - 2 : these pins are used to select one of up to 8 devices of the same type on the same two - wire bus. to select the device , the address value on the two pins must match the corresponding b its contained in the slave address. the address pins are pulled down internally. sda i/o serial data/ addres s: this is a bi - directional pin for the two - wire interface. it is open - drai n and is intended to be wire - or? d with other devices on the two - wire bus. the input buffer incorporates a s chmitt trigger for noise immunity and the output driver includes slope control for falling edges. a n external pull - up resistor is required. scl input ser ial clock: the serial clock pin for the two - wire interface. data is clocked out of the part on the falling edge, and in to the device on the rising edge. the scl input also incorporates a schmitt trigger input for noise immunity. wp input write protect: when tied to vdd, addresses in the entire memory m ap will be write - protected. when wp is connected to ground, all addresses may be written. this pin is pulled down internally. vdd supply supply voltage vss supply ground address latch 1 k x 64 fram array data latch 8 sda counter serial to parallel converter control logic scl wp a 0 - a 2
fm24cl64b - 64kb 3v i2c f - ram (automotive temp.) rev. 1.1 june 2 011 page 3 of 12 overview the fm24cl64b is a serial f - ram memory. the memory array is logically or ganized as a 8,192 x 8 bit memory array and is accessed using an industry standard two - wire interface. functional operation of the f - ram is similar to serial eeproms. the major difference between the fm24cl64b and a serial eeprom with the same pinout relat es to its superior write performance . memory architecture when accessing the fm 24cl 64b , the user addresses 8192 locations each with 8 data bits. these data bits are shifted serially. the 8192 addresses are accessed using the two - wire protocol, which inclu des a slave address (to disting uish other non - mem ory devices) and a 2 - byte address. only the lower 13 bits are used by the decoder for accessing the memory. the upper three address bits should be set to 0 for compatibility with higher density devices in t he future . the access time for memory operation is essentially zero beyond the time needed for the serial protocol. that is, the memory is read or written at the speed of the two - wire bus. unlike an eeprom, it is not necessary to poll the device for a rea dy condition since writes occur at bus speed. that is, by the time a new bus transaction can be shifted into the part, a write operation will be complete. this is explained in more detail in the interface section below. users expect several obvious syste m benefits from the fm 24cl 64b due to its fast write cycle and high endurance as compared with eeprom. however there are less obvious benefits as well. for example in a high noise environment, the fast - write operation is less susceptible to corruption than an eeprom since it is completed quickly. by contrast, an eeprom requiring milliseconds to write is vulnerable to noise during much of the cycle. note that it is the user?s responsibility to ensure that v dd is within data sheet tolerances to prevent incorr ect operation. two - wire interface the fm 24cl 64b employs a bi - directional two - wire bus protocol using few pins or board space. figure 2 illustrates a typical system configuration using the fm 24cl 64b in a microcontroller - based system. the industry standard two - wire bus is familiar to many users but is described in this section. by convention, any device that is sending data onto the bus is the transmitter while the target device for this data is the receiver. the device that is controlling the bus is the master. the master is responsible for generating the clock signal for all operations. any device on the bus that is being controlled is a slave. the fm 24cl 64b always is a slave device. the bus protocol is controlled by transition states in the sda and sc l signals. there are four conditions including start, stop, data bit, or acknowledge. figure 3 illustrates the signal conditions that specify the four states. detailed timing diagrams are shown in the electrical specifications section . figure 2. typical system configuration microcontroller sda scl fm 24 cl 64 b a 0 a 1 a 2 sda scl fm 24 cl 64 b a 0 a 1 a 2 vdd rmin = 1 . 1 kohm rmax = tr / cbus
fm24cl64b - 64kb 3v i2c f - ram (automotive temp.) rev. 1.1 june 2 011 page 4 of 12 figure 3. data transfer protocol stop condition a stop condition is indicated when the bus master drives sda from low to high while the scl signal is high. all operatio ns using the fm 24cl 64b should end with a stop condition. if an operation is in progress when a stop is asserted, the operation will be aborted. the master must have control of sda (not a memory read) in order to assert a stop condition. start condition a start condition is indicated when the bus master drives sda from high to low while the scl signal is high. all commands should be preceded by a start condition. an operation in progress can be aborted by asserting a start condition at any time. aborting an operation using the start condition will ready the fm 24cl 64b for a new operation. if during operation the power supply drops below the specified v dd minimum, the system should issue a start condition prior to performing another operation. data/address transfer all data transfers (including addresses) take place while the scl signal is high. except under the two conditions described above, the sda signal should not change while scl is high. acknowledge the acknowledge takes place after the 8 th data bit has been transferred in any transaction. during this state the transmitter should release the sda bus to allow the receiver to drive it. the receiver drives the sda signal low to acknowledge receipt of the byte. if the receiver does not drive sda low, the condition is a no - acknowledge and the operation is aborted. the receiver would fail to acknowledge for two distinct reasons. first is that a byte transfer fails. in this case, the no - acknowledge ceases the current operation so that the part can be address ed again. this allows the last byte to be recovered in the event of a communication error. second and most common, the receiver does not acknowledge to deliberately end an operation. for example, during a read operation, the fm 24cl 64b will continue to pl ace data onto the bus as long as the receiver sends acknowledges (and clocks). when a read operation is complete and no more data is needed, the receiver must not acknowledge the last byte. if the receiver acknowledges the last byte, this will cause the fm 24cl 64b to attempt to drive the bus on the next clock while the master is sending a new command such as stop. slave address the first byte that the fm 24cl 64b expects after a start condition is the slave address. as shown in figure 4, the slave address con tains the device type or slave id , the device select address bits, a page address bit, and a bit that specifies if the transaction is a read or a write. bits 7 - 4 are the device type (slave id) and should be set to 1010b for the fm 24cl 64b . these bits allo w other function types to reside on the 2 - wire bus within an identical address range. bits 3 - 1 are the device select address bits. they must match the corresponding value on the external address pins to select the devic e. up to eight fm 24cl 64b device s can reside on the same two - wire bus by assigning a different address to each. bit 0 is t he read/write bit. r/w=1 indicates a read operation and r/w=0 indicates a write operation. figure 4. slave address 1 0 1 0 a2 r/w slave id 7 6 5 4 3 2 1 0 a1 a0 device select stop (master) start (master) 7 data bits (transmitter) 6 0 data bit (transmitter) acknowledge (receiver) scl sda
fm24cl64b - 64kb 3v i2c f - ram (automotive temp.) rev. 1.1 june 2 011 page 5 of 12 addressing overview after the fm 24cl 64b (as r eceiver) acknowledges the slave address, the master can place the memory address on the bus for a write operation. the address requires two bytes . the first is the msb. since the device uses only 13 address bits, the value of the upper three bits are don?t care. following the msb is the lsb with the remaining eight address bits. the address value is latched internally. each access causes the latched address value to be incremented automatically. the current address is the value that is held in the latch -- either a newly written value or the address following the last access. the current address will be held for as long as power remains or until a new value is written. reads always use the current address. a random read address can be l oaded by beginning a writ e operation as explained below. after transmission of each data byte, just prior to the acknowledge, the fm24cl64b increments the internal address latch. this allows the next sequential byte to be accessed with no additional addre ssing. after the last address (1fffh) is reached, the address latch will roll over to 0000h. there is no limit to the number of bytes that can be accessed with a single read or write operation . data transfer after the address information has been transmit ted, data transfer between the bus master and the fm 24cl 64b can begin. for a read operation the fm 24cl 64b will place 8 data bits on the bus then wait for an acknowledge from the master. if the acknowledge occurs, the fm 24cl 64b will transfer the next sequen tial byte. if the acknowledge is not sent, the fm 24cl 64b will end the read operation. for a write operation, the fm 24cl 64b will accept 8 data bits from the master then send an acknowledge. all data transfer occurs msb (most significant bit) first. memory operation the fm 24cl 64b is designed to operate in a manner very similar to other 2 - wire interface memory products. the major differences result from the higher performance write capability of f - ram technology. these improvements result in some differences between the fm 24cl 64b and a similar configuration eeprom during writes. the complete operation for both writes and reads is explained below. write operation all writes begin with a slave address , then a memory address. the bus master indicates a write op eration by setting the lsb of the slave address (r/w bit) to a ? 0 ? . after addressing, the bus master sends each byte of data to the memory and the memory generates an acknowledge condition. any number of sequential bytes may be written. if the end of the a ddress range is reached internally, the address counter will wrap from 1fffh to 0000h . unlike other nonvolatile memory technologies, there is no effective write delay with f - ram . since the read and write access times of the underlying memory are the same, the user experiences no delay through the bus. the entire memory cycle occurs in less time than a single bus clock. therefore, any operation including read or write can occur immediately following a write. acknowledge polling, a technique used with eeprom s to determine if a write is complete is unnecessary and will always return a ready condition. internally, an actual memory write occurs after the 8 th data bit is transferred. it will be complete before the acknowledge is sent. therefore, if the user des ires to abort a write without altering the memory contents, this should be done using start or stop condition prior to the 8 th data bit. the fm 24cl 64b uses no page buffering. the memory array can be write - protected using the wp pin . setting the wp pin to a high condition (v dd ) will write - protect all addresses. the fm 24cl 64b will not acknowledge data bytes that are written to protected addresses. in addition, the address counter will not increment if writes are attempted to these addresses. setting wp to a low state (v ss ) will deactivate this feature. wp is pulled down internally. figures 5 and 6 below illustrate a single - byte and multiple - byte write cycles.
fm24cl64b - 64kb 3v i2c f - ram (automotive temp.) rev. 1.1 june 2 011 page 6 of 12 figure 5. single byte write fi gure 6. multiple byte write read operation there are two basic types of read operations. they are current address read and selective address read. in a current address read, the fm 24cl 64b uses the internal address latch to supply the address. in a sele ctive read, the user performs a procedure to set the address to a specific value. current address & sequential read as mentioned above the fm 24cl 64b uses an internal latch to supply the address for a read operation. a current address read uses the existin g value in the address latch as a starting place for the read operation. the system reads from the address immediately following that of the last operation. to perform a current address read, the bus master supplies a slave address with the lsb set to a ? 1 ? . this indicates that a read operation is requested. after receiving the complete slave address , the fm 24cl 64b will begin shifting out data from the current address on the next clock. the current address is the value held in the internal address latch. beginning with the current address, the bus master can read any number of bytes. thus, a sequential read is simply a current address read with multiple byte transfers. after each byte the internal address counter will be incremented. each time the bus master acknowledges a byte, this indicates that the fm 24cl 64b should read out the next sequential byte. there are four ways to properly terminate a read operation. failing to properly terminate the read will most likely create a bus contention as the fm 2 4cl 64b attempts to read out additional data onto the bus. the four valid methods are: 1. the bus master issues a no - acknowledge in the 9 th clock cycle and a stop in the 10 th clock cycle. this is illustrated in the diagrams below. this is preferred. 2. the bus master issues a no - acknowledge in the 9 th clock cycle and a start in the 10 th . 3. the bus master issues a stop in the 9 th clock cycle. 4. the bus master issues a start in the 9 th clock cycle. if the internal address reaches 1fffh, it will wrap around to 0000h on the next read cycle. figures 7 and 8 below show the proper operation for current address reads . selective (random) read there is a simple technique that allows a user to select a random address location as the starting point for a read operation. this involves using the first three bytes of a write operation to set the internal address followed by subsequent read operations. s a slave address 0 address msb a data byte a p by master by f - ram start address & data stop acknowledge address lsb a s a slave address 0 address msb a data byte a p by master by f - ram start address & data stop acknowledge address lsb a data byte a
fm24cl64b - 64kb 3v i2c f - ram (automotive temp.) rev. 1.1 june 2 011 page 7 of 12 to perform a selective read, the bus master sends out the slave address with the lsb set to 0. this specifies a write operation . according to the write protocol, the bus master then sends the address bytes that are loaded into the internal address latch. after the fm 24cl 64b acknowledges the address, the bus master issues a start condition. this simultaneously aborts the write oper ation and allows the read command to be issued with the slave address lsb set to a ? 1 ? . the operation is now a current address read. figure 7. current address read figure 8. sequential read figure 9. selective (random) read s a slave address 1 data byte 1 p by master by f - ram start address stop acknowledge no acknowledge data s a slave address 1 data byte 1 p by master by f - ram start address stop acknowledge no acknowledge data data byte a acknowledge s a slave address 1 data byte 1 p by master by f - ram start address stop no acknowledge data s a slave address 0 address msb a start address acknowledge address lsb a
fm24cl64b - 64kb 3v i2c f - ram (automotive temp.) rev. 1.1 june 2 011 page 8 of 12 electrical specifications absolute maximum ratings symbol description ratings v dd power supply voltage with respect to v ss - 1.0v to + 4.5 v v in voltage on any pin with respect to v ss - 1.0v to + 4.5 v and v in < v dd +1.0v * t stg storage temperature - 55 ? c to +12 5 ? c t lead lead t emperature (soldering, 10 seconds) 26 0 ? c v esd electrostatic discharge voltage - human body model ( aec - q100 - 002 rev. e ) - charged device model ( aec - q100 - 011 rev. b ) - machine model ( a ec - q100 - 003 rev. e ) 4kv 1.25kv 300v package moisture sensitivity level msl - 1 * exception: the v in < v dd +1.0v restriction does not apply to the scl and sda inputs. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational secti on of this specification is not implied. exposure to absolute maximum ratin gs conditions for extended periods may affect device reliability. dc operating conditions (t a = - 40 ? c to + 125 ? c, v dd = 3.0 v to 3.6 v unless otherwise specified) symbol parameter min typ max units notes v dd main power supply 3.0 3.3 3.6 v i dd v dd suppl y current @ scl = 100 khz @ scl = 400 k hz @ scl = 1 mhz 1 20 20 0 34 0 ? a ? a ? a 1 i sb standby current @ +85 ? c @ +125 ? c - - 6 20 ? a ? a 2 i li input leakage current 1 ? a 3 i lo output leakage current 1 ? a 3 v il input low voltage - 0.3 0.2 5 v dd v v ih input high voltage 0.7 5 v dd v dd + 0.3 v v ol output low voltage ( i ol = 3 ma ) 0.4 v r in address input resistance (wp, a2 - a 0 ) for v in = v il (max) for v in = v ih (min) 4 0 1 k ? m ? 5 v hys input hysteresis 0.05 v dd v 4 notes 1. scl to ggling between v dd - 0. 2 v and v ss , other inputs v ss or v dd - 0. 2 v. 2. scl = sda = v dd . all inputs v ss or v dd . stop command issued. 3. vin or vout = v ss to v dd . does not apply to wp, a2 - a 0 pins . 4. this parameter is characterized but not tested. 5. the input pull - down circ uit is strong er (4 0k ? ) when the input voltage is below v il and weak (1m ? ) when the input voltage is above v ih .
fm24cl64b - 64kb 3v i2c f - ram (automotive temp.) rev. 1.1 june 2 011 page 9 of 12 a c parameters (t a = - 40 ? c to + 125 ? c, v dd = 3.0 v to 3.6 v unless otherwise specified) symbol parameter min max min max min max units notes f sc l scl clock frequency 0 100 0 400 0 1000 khz 1 t low clock low period 4.7 1.3 0.6 ? s t high clock high period 4.0 0.6 0.4 ? s t aa scl low to sda data out valid 3 0.9 0.55 ? s t buf bus free before new transmission 4.7 1.3 0.5 ? s t hd:sta sta rt condition hold time 4.0 0.6 0.25 ? s t su:sta start condition setup for repeated start 4.7 0.6 0.25 ? s t hd:dat data in hold 0 0 0 ns t su:dat data in setup 250 100 100 ns t r input rise time 1000 300 300 ns 2 t f input fall time 300 300 100 ns 2 t su:sto stop condition setup 4.0 0.6 0.25 ? s t dh data output hold (from scl @ v il ) 0 0 0 ns t sp noise suppression time constant on scl, sda 50 50 50 ns notes : all scl specifications as well as start and stop conditions appl y to both read and write operations. 1. the speed - related specifications are guaranteed characteristic points along a continuous cur ve of operation from dc to f scl (max) . 2. this parameter is periodically sampled and not 100% tested. capacitance (t a = 25 ? c, f=1.0 mhz, v dd = 3 .3 v) symbol parameter min max units notes c i/o input/output capacitance (sda) - 8 pf 1 c in input capacitance - 6 pf 1 notes 1. this parameter is periodically sampled and not 100% tested. power cycle timing power cycle timing ( t a = - 40 ? c to + 125 ? c, v dd = 3.0 v to 3.6v) symbol parameter min max units notes t pu power up (v dd min) to first access (start condition) 10 - ms t pd last access (stop condition) to power down (v dd min) 0 - ? s t vr v dd rise time 3 0 - ? s/v 1 t vf v dd fall time 100 - ? s/v 1 notes 1. slope measured at any point on v dd waveform. v d d m i n . v d d s d a , s c l t v r t p d t p u t v f
fm24cl64b - 64kb 3v i2c f - ram (automotive temp.) rev. 1.1 june 2 011 page 10 of 12 ac test conditions equivalent ac test load circuit input pulse levels 0.1 v dd to 0.9 v dd input rise and fall times 10 ns input and output timing levels 0.5 v dd diagram notes all start and stop timing parameters apply to both read and write cycles. clock specifications are identical for read and write cycles. write timing parameters apply to slave address, word address, and write data bits. functional relati onships are illustrated in the relevant datasheet sections. these diagrams illustrate the timing parameters only. read bus timing write bus timing data retention parameter min max units notes data retention @ t a = +5 5 ? @ t a = +105 ? @ t a = +125 ? note: data retention qualification tests are accelerated tests and are performed such that all three conditions have been ap plied: (1) 17 years at a t emperature of +55 ? c, (2) 10,000 hours at +105 ? c, and (3) 1,000 hours at +125 ? c. t su:sda start t r ` t f stop start t buf t high 1/fscl t low t sp t sp acknowledge t hd:dat t su:d at t aa t dh scl sda t su:sto start stop start acknowledge t aa t hd:dat t hd:sta t su:dat scl sda typical grade 1 operating profile 0 200 400 600 800 1000 1200 1400 1600 70 75 80 85 90 95 100 105 110 115 120 125 temperature (c) hours typical grade 1 storage profile 0 5000 10000 15000 20000 25000 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 temperature (c) hours 3 . 6 v output 1 . 8 k ohm 100 pf
fm24cl64b - 64kb 3v i2c f - ram (automotive temp.) rev. 1.1 june 2 011 page 11 of 12 mechanical drawing 8 - pin soic (jedec standard ms - 012 variation aa) refer to jedec ms - 012 for complete dimensions and notes. all dimensio ns in millimeters . soic package marking scheme legend: xx x xx= part number , p=package type r=rev code, lllllll= lot code ric=ramtron int?l corp, yy=year, ww=work week example: fm 24cl64b - ga, green soic , automotive temperature, rev a, l ot l3502g1, year 2011, work week 04 24cl64b ga al3502g1 ric1104 xxxx xx - p rll llll l ricyyww p i n 1 3 . 9 0 0 . 1 0 6 . 0 0 0 . 2 0 4 . 9 0 0 . 1 0 0 . 1 0 0 . 2 5 1 . 3 5 1 . 7 5 0 . 3 3 0 . 5 1 1 . 2 7 0 . 1 0 m m 0 . 2 5 0 . 5 0 4 5 0 . 4 0 1 . 2 7 0 . 1 9 0 . 2 5 0 - 8 r e c o m m e n d e d p c b f o o t p r i n t 7 . 7 0 0 . 6 5 1 . 2 7 2 . 0 0 3 . 7 0
fm24cl64b - 64kb 3v i2c f - ram (automotive temp.) rev. 1.1 june 2 011 page 12 of 12 revision history revision date summary 1 .0 2 / 22/2011 initial release 1.1 6/2/2011 added esd ratings. fixed notes 4 and 5 in dc table.

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